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As the number of transistors on a chip increases exponentially, designs are growing increasingly complex.  Our ability to effectively design and verify extremely high gate count designs lags the rate at which we can add design complexity.    Power is now the limiting factor in chip design.  In effect, there is a need for efficient hardware, i.e., high performance low energy ASICs.  Such efficient designs are currently expensive.  The Rethinking Digital Design team is  pursuing new aproaches to digital design by considering ways to amortize non-recurring design and verification costs.

  

  

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