https://sites.google.com/a/stanford.edu/fpgen/home
The floating-point unit generator, FPGen, is a parameterized generator for generating energy and area efficient designs and codifying FPU designers’ knowledge. The generator was developed within the research effort to rethink digital design and showcase the utility of building chip generators instead of chips. The FPU generator came as the coronation of our earlier work on how to build energy-efficient FPUs both for throughput machines such as GPUs and latency machines such as CPUs. The generator was built using the Genesis 2 framework.
* Mark Horowitz
* Sameh Galal
* Ofer Shacham
* Jing Pu
* John S. Brunhaver II
* Artem Vassiliev
* Zain Asgar
[1] Galal, Sameh, Ofer Shacham, J. S. Brunhaver, Jing Pu, Artem Vassiliev, and Mark Horowitz. “FPU Generator for Design Space Exploration.” In Computer Arithmetic (ARITH), 2013 21st IEEE Symposium on, pp. 25-34. IEEE, 2013.